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120 ma, current sinking, 10-bit, i 2 c dac ad5398 features 120 ma current sink available in 8-lead lfcsp package 2-wire (i 2 c?-compatible) serial interface 10-bit resolution integrated current sense resistor 2.7 v to 5.5 v power supply guaranteed monotonic over all codes power-down to 0.5 a typical internal reference ultralow noise preamplifier power-down function power-on reset consumer applications lens autofocus image stabilization optical zoom shutters iris/exposure neutral density filter ndfs lens covers camera phones digital still cameras camera modules digital video cameras (dvcs)/camcorders camera-enabled devices security cameras web/pc cameras industrial applications heater control fan control cooler (peltier) control solenoid control valve control linear actuator control light control current loop control functional block diagram 05034-001 power-on reset 3 sda 7 agnd 2 dgnd 6 v dd 4 scl 1 pd 8 i sink r sense 3.3 i 2 c serial interface 10-bit current output dac reference r ad5398 5 dgnd figure 1. general description the ad5398 is a single 10-bit dac with 120 ma output current sink capability. it feat ures an internal reference and operates from a single 2.7 v to 5.5 v supply. the dac is controlled via a 2-wire (i 2 c-compatible) serial interface that operates at clock rates up to 400 khz. the ad5398 incorporates a power-on reset circuit, which ensures that the dac output po wers up to 0 v and remains there until a valid write takes place. it has a power-down feature that reduces the current consumption of the device to 1 a max. the ad5398 is designed for auto focus, image st abilization, and optical zoom applications in camera phones, digital still cameras, and camcorders. the ad5398 also has many industrial applications, such as controlling temperature, light, and movement, over the range ? 40c to +85c without derating. the i 2 c address range for the ad5398 is 0x18 to 0x1f inclusive. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved.
ad5398 rev. a | page 2 of 16 table of contents specifications ..................................................................................... 3 ac specifications .......................................................................... 4 timing specifications .................................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 ter mi nolo g y ...................................................................................... 9 theory of operation ...................................................................... 10 serial interface ............................................................................ 10 i 2 c bus operation ...................................................................... 10 data format ................................................................................ 10 power supply bypassing and grounding ................................ 11 applications ..................................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 7/05rev. 0 to rev. a changes to table 4............................................................................ 5 deleted figure 21............................................................................ 13 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14 12/04revision 0: initial version
ad5398 rev. a | page 3 of 16 specifications v dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v, load resistance r l = 25 connected to v dd ; all specifications t min to t max , unless otherwise noted. table 1. b version 1 parameter min typ max unit test conditions/comments dc performance v dd = 3.6 v to 4.5 v; device operates over 2.7 v to 5.5 v with reduced performance resolution 10 bits 117 a/lsb relative accuracy 2 1.5 4 lsb differential nonlinearity 2, 3 1 lsb guaranteed monotonic over all codes zero code error 2, 4 0 1 5 ma all 0s loaded to dac offset error @ code 16 2 0.5 ma gain error 2 0.6 % of fsr @ 25c offset error drift 4, 5 10 a/oc gain error drift 2, 5 0.2 0.5 lsb/oc output characteristics minimum sink current 4 3 ma maximum sink current 120 ma v dd = 3.6 v to 4.5 v; device operates over 2.7 v to 5.5 v but specified maximum sink current might not be achieved output current during pd 80 na pd = 1 output compliance 5 0.6 v dd v output voltage range over which max sink current is available power-up time 20 s to 10% of fs, coming out of power-down mode; v dd = 5 v logic inputs (pd) 5 input current 1 a input low voltage, v inl 0.8 v v dd = 2.7 v to 5.5 v input high voltage, v inh 0.7 v dd v v dd = 2.7 v to 5.5 v pin capacitance 3 pf logic inputs (scl, sda) 5 input low voltage, v inl ?0.3 0.3 v dd v input high voltage, v inh 0.7 v dd v dd + 0.3 v input leakage current i in 1 a v in = 0 v to v dd input hysteresis, v hyst 0.05 v dd v digital input capacitance, c in 6 pf glitch rejection 6 50 ns pulse width of spike suppressed power requirements v dd 2.7 5.5 v i dd (normal mode) i dd specification is valid for all dac codes. v dd = 2.7 v to 5.5 v v dd = 2.7 v to 4.5 v 2.5 2.3 4 3 ma ma v ih = v dd , v il = gnd, v dd = 5.5 v v ih = v dd , v il = gnd, v dd = 4.5 v i dd (power-down mode) 0.5 1 a v ih = v dd , v il = gnd 1 temperature range is as follows: b version: C40c to +85c. 2 see the terminology section. 3 linearity is tested using a redu ced code range: codes 32 to 1023. 4 to achieve near zero output c urrent, use the power-down feature. 5 guaranteed by design and characterization; not production tested. 6 input filtering on both the scl and sda inputs suppresses noise spikes that are less than 50 ns.
ad5398 rev. a | page 4 of 16 ac specifications v dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v, load resistance r l = 25 connected to v dd , unless otherwise noted. table 2. b version 1 , 2 parameter min typ max unit test conditions/comments output current settling time 250 s v dd = 5 v, r l = 25 , l l = 680 h ? scale to ? scale change (0x100 to 0x300) slew rate 0.3 ma/s major code change glitch impulse 0.15 na-s 1 lsb change around major carry digital feedthrough 3 0.06 na-s 1 temperature range is as follows: b version: C40c to +85c. 2 guaranteed by design and characterization; not production tested. 3 see the terminology section. timing specifications v dd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. table 3. b version parameter 1 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 2 0.9 s max t hd,dat , data hold time 0 s min t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop condition and a start condition t 10 300 ns max t r, rise time of both scl and sda when receiving 0 ns min may be cmos driven t 11 250 ns max t f , fall time of sda when receiving 300 ns max t f , fall time of both scl and sda when transmitting 20 + 0.1 c b 3 ns min c b 400 pf max capacitive load for each bus line 1 guaranteed by design and characterization; not production tested. 2 a master device must provide a hold time of at least 300 ns for the sda signal (ref erred to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 3 c b is the total capacitance of one bus line in pf. t r and t f are measured between 0.3 v dd and 0.7 v dd. 05034-002 sda t 9 scl t 3 t 10 t 11 t 4 t 4 t 6 t 2 t 5 t 7 t 1 t 8 start condition repeated start condition stop condition figure 2. 2-wire serial interface timing diagram
ad5398 rev. a | page 5 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. 1 table 4. parameter rating v dd to agnd C0.3 v to +7 v v dd to dgnd C0.3 v to v dd + 0.3 v agnd to dgnd C0.3 v to +0.3 v scl, sda to dgnd C0.3 v to v dd + 0.3 v pd to dgnd C0.3 v to v dd + 0.3 v i sink to agnd C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature (t j max) 150c lfcsp power dissipation (t j max C t a )/ ja ja thermal impedance 2 mounted on 2-layer board 84c/w mounted on 4-layer board 48c/w lead temperature, soldering max peak reflow temperature 3 260c (5c) 1 transient currents of up to 100 ma do not caus e scr latch-up. 2 to achieve the optimum ja , it is recommended that the ad5398 is soldered on a 4-layer board. the ad5398 comes in an 8-lead lfcsp package with an exposed paddle that should be connected to the same potential as the ad5398 dgnd pin. 3 as per jedec j-std-020c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution esd (electrostatic discharge) sensiti ve device. electrostatic charges as hi gh as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5398 rev. a | page 6 of 16 pin configuration and fu nction descriptions 05034-003 ad5398 top view (not to scale) pd 1 dgnd 2 sda 3 scl 4 i sink agnd v dd dgnd 8 7 6 5 figure 3. pin configuration table 5. pin function descriptions pin no. nemonic description 1 pd power down. asynchronous power-down signal. 2 dgnd digital ground pin. 3 sda i 2 c interface signal. 4 scl i 2 c interface signal. 5 dgnd digital ground pin. 6 v dd digital supply voltage. 7 agnd analog ground pin. 8 i sink output current sink.
ad5398 rev. a | page 7 of 16 typical performance characteristics 2.0 ?0.5 0 0.5 1.0 1.5 inl v dd = 3.8v temp = 25 c 1008 1023 952 896 840 784 728 672 616 560 504 448 392 336 280 224 168 112 56 0 05034-004 code inl (lsb) figure 4. typical inl plot 1008 1023 952 896 840 784 728 672 616 560 504 448 392 336 280 224 168 112 56 0 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 05034-005 code dnl (lsb) dnl v dd = 3.8v temp = 25 c figure 5. typical dnl plot 91.5 92.0 91.0 90.5 90.0 89.5 89.0 88.5 88.0 300.0 ?6 333.1 ?6 250.0 ?6 200.0 ?6 150.0 ?6 100.0 ?6 53.5 ?6 05034-006 time output current (ma) figure 6. ? to ? scale settling time (v dd = 3.6 v) 05034-007 ch3 m50.0 s vert = 50 s/div horiz = 468 a/div 3 figure 7. settling time for a 4-lsb step (v dd = 3.6 v) 05034-008 ch1 m2.0s vert = 2 a/div 4.8 a p-p horiz = 2s/div 1 figure 8. 0.1 hz to 10 hz noise plot (v dd = 3.6 v) 1008 1023 952 896 840 784 728 672 616 560 504 448 392 336 280 224 168 112 56 0 0.14 0.12 i out @ +25c i out @ +85c i out @ ?40c 0.10 0.08 0.06 0.04 0.02 0 05034-009 code i out (a) figure 9. sink current vs. code vs. temperature (v dd = 3.6 v)
ad5398 rev. a | page 8 of 16 2000 1800 1600 1400 1200 1000 800 600 400 200 0 10 100 1k 100k 10k 05034-010 frequency a/v figure 10. ac power supply rejection (v dd = 3.6 v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 85 ?40?30?20?100 15253545556575 ?1.0 05034-011 temperature ( c) inl (lsb) positive inl (v dd = 3.6v) positive inl (v dd = 4.5v) positive inl (v dd = 3.8v) negative inl (v dd = 3.6v) negative inl (v dd = 4.5v) negative inl (v dd = 3.8v) figure 11. inl vs. temperature vs. supply 1.0 85 ?40?30?20?100 15253545556575 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 05034-012 temperature ( c) dnl (lsb) positive dnl (v dd = 3.6v) positive dnl (v dd = 4.5v) positive dnl (v dd = 3.8v) negative dnl (v dd = 3.6v) negative dnl (v dd = 4.5v) negative dnl (v dd = 3.8v) figure 12. dnl vs. temperature vs. supply 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.05 0.10 85 ?40?30?20?100 15253545556575 0 05034-013 temperature ( c) zero code error (ma) v dd = 3.6v v dd = 3.8v v dd = 4.5v figure 13. zero code error vs. supply voltage vs. temperature 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 85 ?40?30?20?100 15253545556575 ?2.0 05034-096 temperature ( c) fs error (ma) v dd = 3.6v v dd = 3.8v v dd = 4.5v figure 14. full-scale error vs. temperature vs. supply
ad5398 rev. a | page 9 of 16 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 4 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot is shown in figure 5 . zero-code error zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally the output is 0 ma. the zero-code error is always positive in the ad5398 because the output of the dac cannot go below 0 ma. this is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in ma. gain error this is a measurement of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percent of the full-scale range. gain error drift this is a measurement of the change in gain error with changes in temperature. it is expressed in lsb/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in na-s and is measured when the digital input code is changed by 1 lsb at the major carry transition. digital feedthrough digital feedthrough is a measurement of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in na-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. offset error offset error is a measurement of the difference between i sink (actual) and i out (ideal) in the linear region of the transfer function, expressed in ma. offset error is measured on the ad5398 with code 16 loaded into the dac register. offset error drift this is a measurement of the change in offset error with a change in temperature. it is expressed in v/c.
ad5398 rev. a | page 10 of 16 theory of operation the ad5398 is a fully integrated 10-bit dac with 120 ma output current sink capability and is intended for driving voice coil actuators in applications such as lens autofocus, image sta- bilization, and optical zoom. the circuit diagram is shown in figure 15 . a 10-bit current output dac coupled with resistor r generates the voltage that drives the noninverting input of the operational amplifier. this voltage also appears across the r sense resistor and generates the sink current required to drive the voice coil. resistors r and r sense are interleaved and matched. therefore, the temperature coefficient and any nonlinearities over tem- perature are matched and the output drift over temperature is minimized. diode d1 is an output protection diode. 05034-015 power-on reset 3 sd a 7 agnd 2 dgnd 6 v dd 4 scl 1 pd 8 i sink v bat voice coil actuator d1 r sense 3.3 i 2 c serial interface 10-bit current output dac reference r ad5398 5 dgnd figure 15. block diagram showing connection to voice coil serial interface the ad5398 is controlled using the industry-standard i 2 c 2-wire serial protocol. data can be written to the dac, or read back from it, at data rates up to 400 khz. after a read operation the contents of the input register are reset to all zeros. i 2 c bus operation an i 2 c bus operates with one or more master devices that generate the serial clock (scl), and read/write data on the serial data line (sda) to/from slave devices such as the ad5398. all devices on an i 2 c bus have their scl pin connected to the sda line and their scl pin connected to the scl line. i 2 c devices can only pull the bus lines low; pulling high is achieved by pull- up resistors r p . the value of r p depends on the data rate, bus capacitance, and the maximum load current that the i 2 c device can sink (3 ma for a standard device). 05034-016 scl sda i 2 c master device ad5398 i 2 c slave device i 2 c slave device r p r p v dd figure 16. typical i 2 c bus when the bus is idle, scl and sda are both high. the master device initiates a serial bus operation by generating a start condition, which is defined as a high-to-low transition on the sda low while scl is high. the slave device connected to the bus responds to the start condition and shifts in the next eight data bits under control of the serial clock. these eight data bits consist of a 7-bit address, plus a read/write bit, which is 0 if data is to be written to a device, and 1 if data is to be read from a device. each slave device on an i 2 c bus must have a unique address. the address of the ad5398 is 0001100; however, 0001101, 0001110, and 0001111 address the part because the last two bits are unused/dont care (see figure 17 and figure 18 ). since the address plus r/w bit always equals eight bits of data, another way of looking at it is that the write address of the ad5398 is 0001 1000 (0x18) and the read address is 0001 1001 (0x19). again, bit 6 and bit 7 of the address are unused, and therefore the write addresses can also be 0x1a, 0x1c, and 0x1e, and the read address can be 0x1b, 0x1d, and 0x1f (see figure 17 and figure 18 ). at the end of the address data, after the r/w bit, the slave device that recognizes its own address responds by generating an acknowledge (ack) condition. this is defined as the slave device pulling sda low while scl is low before the ninth clock pulse, and keeping it low during the ninth clock pulse. upon receiving ack, the master device can clock data into the ad5398 in a write operation, or it can clock it out in a read operation. data must change only during the low period of the clock, because sda transitions during the high period define a start condition as described previously, or a stop condition as described in the data format section. i 2 c data is divided into blocks of eight bits, and the slave generates an ack at the end of each block. since the ad5398 requires 10 bits of data, two data-words must be written to it when a write operation, or read back from it when a read operation. at the end of a read or write operation, the ad5398 acknowledges the second data byte. the master generates a stop condition, defined as a low-to-high transition on sda while scl is high, to end the transaction. data format data is written to the ad5398 high byte first, msb first, and is shifted into the 16-bit input register. after all data is shifted in, data from the input register is transferred to the dac register. because the dac requires only 10 bits of data, not all bits of the input register data are used. the msb is reserved for an active- high, software-controlled, power-down function. bit 14 is unused; bit 13 to bit 4 are dac data; bit 9 to bit 0 and bit 3 to bit 0 are unused. during a read operation, data is read back in the same bit order.
ad5398 rev. a | page 11 of 16 05034-017 pd x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 00 scl sd a start by master ack by ad5398 11 91 ack by ad5398 ack by ad5398 stop by master frame 3 least significant data byte frame 2 most significant data byte frame 1 serial bus address byte 0 1 1 x x r/w 9 figure 17. write operation 05034-018 pd x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 00 scl sd a start by master ack by ad5398 11 91 ack by ad5398 ack by ad5398 stop by master frame 3 least significant data byte frame 2 most significant data byte frame 1 serial bus address byte 0 1 1 x x r/w 9 figure 18. read operation table 6. data format 1 serial data-words high byte low byte serial data bits sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 input register r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 function pd x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 1 pd = soft power-down; x = unused/dont care; d9 to d0 = dac data power supply bypassing and grounding when accuracy is important in an application, it is beneficial to consider power supply and ground return layout on the pcb. the pcb for the ad5398 should have separate analog and digital power supply sections. where shared agnd and dgnd is necessary, the connection of grounds should be made at only one point, as close as possible to the ad5398. special attention should be paid to the layout of the agnd return path and track between the voice coil motor and i sink to minimize any series resistance. figure 19 shows the output current sink of the ad5398 and illustrates the importance of reducing the effective series impedance of agnd, and the track resistance between the motor and i sink . the voice coil is modeled as inductor l c and resistor r c . the current through the voice coil is effectively a dc current that results in a voltage drop, v c , when the ad5398 is sinking current; the effect of any series inductance is minimal. the maximum voltage drop allowed across r sense is 400 mv, and the minimum drain to source voltage of q1 is 200 mv. this means that the ad5398 output has a compliance voltage of 600 mv. if v drop falls below 600 mv, the output transistor, q1, can no longer operate properly and i sink might not be maintained as a constant. 05034-019 7 agnd v g q1 ground resistance ground inductance 8 i sink r sense 3.3 r g l g v drop v t v c v bat r t r c l c trace resistance voice coil actuator figure 19. effect of pcb trace resistance and inductance
ad5398 rev. a | page 12 of 16 as the current increases through the voice coil, v c increases and v drop decreases and eventually approaches the minimum specified compliance voltage of 600 mv. the ground return path is modeled by the components r g and l g , and the track resistance between the voice coil and the ad5398 is modeled as r t . the inductive effects of l g influence r sense and r c equally, and because the current is maintained as a constant, it is not as critical as the purely resistive component of the ground return path. when the maximum sink current is flowing through the motor, the resistive elements, r t and r g , might have an impact on the voltage headroom of q1 and could, in turn, limit the maximum value of r c because of voltage compliance. for example, v bat = 3.6 v r g = 0.5 r t = 0.5 i sink = 120 ma v drop = 600 mv (the compliance voltage) then the largest value of resistance of the voice coil, r c , is = ++? = sin k gsink t sink drop bat c i ririvv r )] ()([ 24 ma120 )]0.5ma(1202mv[600v3.6 = +? for this reason it is important to minimize any series impedance on both the ground return path and interconnect between the ad5398 and the motor. the power supply of the ad5398 should be decoupled with 0.1 f and 10 f capacitors. these capacitors should be kept as physically close as possible, with the 0.1 f capacitor serving as a local bypass capacitor, and therefore should be located as close as possible to the v dd pin. the 10 f capacitor should be a tantalum bead-type; the 0.1 f capacitor should be a ceramic type with a low effective series resistance and effective series inductance. the 0.1 f capacitor provides a low impedance path to ground for high transient currents. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is to use a multilayer board with ground and power planes, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board. the exposed paddle on the ad5398 should be soldered to ground to ensure the best possible thermal performance. the thermal impedance of the ad5398 lfcsp package is 48c/w when soldered in a 4-layer board. it is defined in the absolute maximum ratings section.
ad5398 rev. a | page 13 of 16 applications the ad5398 is designed to drive both spring preloaded and nonspring linear motors used in applications such as lens auto- focus, image stabilization, or optical zoom. the operation principle of the spring preloaded motor is that the lens position is controlled by the balancing of a voice coil and spring. figure 20 shows the transfer curve of a typical spring preloaded linear motor for autofocus. the key points of this transfer function are displacement or stroke, which is the actual distance the lens moves in mm, and the current through the motor in ma. a start current is associated with spring preloaded linear motors, which is effectively a threshold current that must be exceeded for any displacement in the lens to occur. the start current is usually 20 ma or greater; the rated stroke or displacement is usually 0.25 mm to 0.4 mm; and the slope of the transfer curve is approximately 10 m/ma or less. the ad5398 is designed to sink up to 120 ma, which is more than adequate for available commercial linear motors or voice coils. another factor that makes the ad5398 the ideal solution for these applications is the monotonicity of the device, which ensures that lens positioning is repeatable for the application of a given digital word. figure 21 shows a typical application circuit for the ad5398. 05034-020 0.5 0.4 0.3 0.2 0.1 0 10 20 30 40 start current 50 60 70 80 90 100 110 120 0 sink current (ma) stroke (mm) figure 20. spring preloaded voic e coil stroke vs. sink current 05034-022 power-on reset 3 7 2 6 4 1 power-down reset 8 voice coil actuator r sense 3.3 i 2 c serial interface 10-bit current output dac reference r ad5398 5 scl sda i 2 c master device i 2 c slave device i 2 c slave device r p r p v dd v dd v cc 0.1 f 10 f + 0.1 f 10 f + figure 21. typical application circuit
ad5398 rev. a | page 14 of 16 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicato r 1.50 ref 0.50 0.40 0.30 2.75 bsc sq top view 12 max 0.70 max 0.65 typ seating plane pin 1 indicator 0.90 max 0.85 nom 0.30 0.23 0.18 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.00 bsc sq 5 8 figure 22. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad5398bcpz-reel 1 C40c to +85c 8-lead lfcsp_vd cp-8-2 ad5398bcpz-reel7 1 C40c to +85c 8-lead lfcsp_vd cp-8-2 ad5398bcpz-wp 1 C40c to +85c 8-lead lfcsp_vd cp-8-2 EVAL-AD5398EB evaluation board 1 z = pb-free part.
ad5398 rev. a | page 15 of 16 notes
ad5398 rev. a | page 16 of 16 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05034C0C7/05(a)

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